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| DATA SHEET BIPOLAR ANALOG INTEGRATED CIRCUIT PC1851B I2C BUS-COMPATIBLE US MTS PROCESSING LSI The PC1851B is an integrated circuit for US MTS (Multiplexed Television Sound) system with the addition of the I2C bus interface. All functions required for US MTS system are incorporated on a single chip. The PC1851B allows users to switch modes, control volume and tone, and adjust the separation circuit through the I2C bus. FEATURES * Stereo demodulation, SAP (Sub Audio Program) demodulation, dbx noise reduction decoding, I2C bus interface, input selector (2 channels), surround processor (1 phase), volume and tone control circuits incorporated on a single chip * Mode switching, volume and tone control, and separation adjustment through the I2C bus * Power supply: 8 V to 10 V * On-chip input attenuator for simple interface with intermediate frequency processing IC (I2C bus control) * Output level: 1.4 Vp-p (with L+R signals, 100 % modulation) APPLICATION * TV sets and VCRs for north America ORDERING INFORMATION Part Number Package 42-pin plastic SDIP (15.24 mm (600)) PC1851BCU The PC1851B is available only to licensees of THAT Corporation. For information, please call: (508) 229-2500 (U.S.A), or (03) 5790-5391 (Tokyo). The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S13417EJ2V0DS00 (2nd edition) Date Published June 2000 N CP(K) Printed in Japan The mark shows major revised points. (c) 1998 PC1851B SYSTEM BLOCK DIAGRAM q TV Tuner IF processing C, Y, and deflecting signal output Chroma output CRT DTS interface Vertical output PC1851B SCL Tuning microcontroller SDA L Remote controller receive amp. R L R MTS processing R L Power amplifier Graphic equalizer (Surround processor) PIN photodiode 2 Data Sheet S13417EJ2V0DS00 PC1851B BLOCK DIAGRAM 9V VCC 1 LOT 26 + ROT 25 21 D/A Volume Control AGND + 10 F 10 F 2200 pF 0.1 F + TLO 31 Tone Control 28 29 30 Surround Block 27 TRO 2200 pF RTC + LTC 32 LBC 33 RBC 0.022 F SUR FOR 40 FOL 41 EL2 EL1 37 Selector Block 19 + + + + + + + 2.2 F + + 2.2 F 0.1 F 39 4.7 F ER2 36 ER1 38 MOL 35 MOR 34 Filter Matrix Block VOL-C Filter Control 1 F 42 1 F 10 F D/A Offset Absorption dbx Noise Reduction Block Deemphasis 20 VOA 16 WTI** 17 MOA WRB 3.3 F 13 STI** 14 SRB 1 F 16.6 k 18 dO + 22 F VRE 2 1/2VCC L+R LPF Switch 15 ITI* 11 SI 0.1 F 0.1 F 1 k + PD2 PD1 D1 D2 4 3 5 6 Input Attenuator I2C Bus Interface D/A Noise BPF Noise Detector Stereo Demodulation Block SAP Demodulation Block I2C Bus Interface 10 SOT 1 F + 4.7 F SDA 22 SCL 23 DGND 24 68 k 9 NDT 0.47 F + + COM 7 SOA 2.2 F 12 SDT 8 0.047 F 0.1 F Remark Use the followings for external parts. Resistor (*): Metal film resistor ( 1 %). Unless otherwise specified; 5 % Capacitors (**): Tantalum capacitor (10 %). Unless otherwise specified; 20 % + 3 k + 5.1 k 1F 1 F Data Sheet S13417EJ2V0DS00 3 PC1851B STEREO DEMODULATION BLOCK D1 5 D2 6 PD1 PD2 3 4 D/A Divider 1 4 1 2 Stereo Phase Comparator Stereo VCO Pilot Discrimination Phase Comparator To I C bus Interface From Input Attenuator Stereo LPF Pilot Canceler L-R AM Demodulator To L+R LPF To Switch 2 SAP DEMODULATION BLOCK From Input Attenuator SAP BPF To Noise BPF SOA 12 Offset Absorption Phase Detector Loop Filter SAP VCO D/A SDT 8 SAP Detector To I C bus Interface 2 SAP LPF 10 SOT 4 Data Sheet S13417EJ2V0DS00 PC1851B dbx NOISE REDUCTION BLOCK From Switch LPF fH Trap 408-Hz LPF 2 fH Trap Spectral RMS Filter Variable Emphasis Spectral RMS 2.19-kHz LPF Wide-band RMS Filter D/A Timing Current D/A Wide-band RMS Offset Absorption Wide-band VCA Offset Absorption To Matrix Block 18 dO 14 13 15 ITI 17 16 20 VOA SRB STI WRB WTI SELECTOR BLOCK ER1 ER2 38 36 From Matrix Block (L-channel signal) From Matrix Block (R-channel signal) Switch Note1 40 k Note2 40 k To Surround Block - + EL1 EL2 39 37 Note2 40 k 40 k To Surround Block Switch (Monaural/Stereo) Notes 1. Switch (TV signal/External input 1/External input 2). 2. The input gain 0 dB/6 dB can be selected by the command of the I2C bus (refer to 4.3 (5) Input gain). Data Sheet S13417EJ2V0DS00 5 PC1851B SURROUND BLOCK To Tone Control Block From Selector Block (L-channel) - Phase Shifter + From Selector Block (R-channel) 27 SUR To Tone Control Block - 6 Data Sheet S13417EJ2V0DS00 PC1851B PIN CONFIGURATION (Top View) 42-pin plastic SDIP (15.24 mm (600)) * PC1851BCU Power Supply (9 V) 1 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 VCC VRE PD1 PD2 MOA FOL FOR EL1 ER1 EL2 ER2 MOL MOR LBC LTC TLO RBC RTC TRO SUR LOT ROT DGND SCL SDA 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 Monaural Offset Absorption L-channel Fixed Output R-channel Fixed Output External L-channel Input 1 External R-channel Input 1 External L-channel Input 2 External R-channel Input 2 L-channel Matrix Output R-channel Matrix Output L-channel Capacity of Low Frequency Band Width L-channel Capacity of High Frequency Band Width L-channel Offset Absorption R-channel Capacity of Low Frequency Band Width R-channel Capacity of High Frequency Band Width R-channel Offset Absorption Surround Timing L-channel Output R-channel Output Digital GND (for I C bus) SCL (for I C bus) SDA (for I C bus) 2 2 2 Vcc Filter Pilot Discrimination Filter 1 Pilot Discrimination Filter 2 Phase Comparator Filter 1 Phase Comparator Filter 2 Composite Signal Input SAP Discrimination Filter Noise Detector Filter SAP Single Output SAP Single Input SAP Offset Absorption Spectral RMS Timing Spectral RMS Offset Absorption Timing Current Setting Wide-band RMS Timing Wide-band RMS Offset Absorption Variable Emphasis Offset Absorption Volume Control Offset Absorption VCA Offset Absorption Analog GND D1 D2 COM SDT NDT SOT SI SOA STI SRB ITI WTI WRB dO VOL-C VOA AGND Data Sheet S13417EJ2V0DS00 7 PC1851B CONTENTS 1. 2. PIN EQUIVALENT CIRCUITS ............................................................................................ 9 BLOCK FUNCTIONS ........................................................................................................ 18 2.1 2.2 2.3 2.4 2.5 Stereo Demodulation Block ................................................................................... 18 SAP Demodulation Block ...................................................................................... 19 dbx Noise Reduction Block ................................................................................... 20 Matrix Block ............................................................................................................ 21 Selector Block ........................................................................................................ 21 3. I2C BUS INTERFACE ....................................................................................................... 22 3.1 3.2 Data Transfer ......................................................................................................... 23 Data Transfer Format ............................................................................................ 24 4. I2C BUS COMMANDS ...................................................................................................... 27 4.1 4.2 4.3 4.4 Subaddress List ..................................................................................................... 27 Setting Procedure .................................................................................................. 29 Explanation of Write Register ................................................................................ 31 Explanation of Read Register ............................................................................... 38 5. 6. 7. MODE MATRIX ................................................................................................................. 40 SELECTOR TABLE .......................................................................................................... 41 USAGE CAUTIONS .......................................................................................................... 42 7.1 7.2 7.3 7.4 7.5 7.6 Caution on Shock Noise Reduction ...................................................................... 42 Supply Voltage ....................................................................................................... 42 Impedance of Input and Output Pins .................................................................... 42 Drive Capability of Output Pins ............................................................................. 42 Caution on External Components ......................................................................... 43 Change of Electrical Characteristics by External Components ........................... 43 8. 9. ELECTRICAL SPECIFICATIONS .................................................................................... 44 TEST CIRCUIT .................................................................................................................. 56 10. PACKAGE DRAWINGS ................................................................................................... 58 11. RECOMMENDED SOLDERING CONDITIONS .............................................................. 59 8 Data Sheet S13417EJ2V0DS00 PC1851B 1. PIN EQUIVALENT CIRCUITS (1/9) Pin No. 1 2 Pin Name Power Supply (9 V) 1 2 Symbol VCC VRE Internal Equivalent Circuit VCC Filter VCC 10 k 10 k 5 k 20 k 20 k 10 k 20 k 2 10 k 20 k 5 k GND 3 Pilot Discrimination Filter 1 PD1 VCC 3 15 k 15 k 5 k 1 VCC 2 4 Pilot Discrimination Filter 2 PD2 VCC 15 k 15 k 5 k 4 Data Sheet S13417EJ2V0DS00 9 PC1851B (2/9) Pin No. 5 Pin Name Phase Comparator Filter 1 Symbol Internal Equivalent Circuit D1 5 VCC 15 k 5 k 5 k 1 VCC 2 6 Phase Comparator Filter 2 D2 VCC 15 k 5 k 5 k 6 7 Composite Signal Input COM VCC 1 VCC 2 80 k 7 3 k 17 k 5 k 5 k GND 8 SAP Discrimination Filter SDT 8 VCC 20 k 10 k 20 k 20 k 10 k GND 10 Data Sheet S13417EJ2V0DS00 PC1851B (3/9) Pin No. 9 Pin Name Noise Detector Filter Symbol NDT Internal Equivalent Circuit 9 VCC 20 k 20 k 20 k 20 k 20 k 20 k 20 k GND 10 SAP Single Output SOT 2 k VCC 200 10 2 k GND Data Sheet S13417EJ2V0DS00 11 PC1851B (4/9) Pin No. 11 Pin Name SAP Single Input Symbol SI Internal Equivalent Circuit 1 VCC 2 VCC 10 k 10 k 80 k 5 k 11 5 pF 5 k GND 12 SAP Offset Absorption SOA VCC 10 k 10 k 5 pF 50 k 3 k 2.3 k 10 k GND 12 13 Spectral RMS Timing STI 5 k 600 VCC 5 k 5 k 5 k 13 5 k GND 12 Data Sheet S13417EJ2V0DS00 PC1851B (5/9) Pin No. 14 Pin Name Spectral RMS Offset Absorption Symbol SRB Internal Equivalent Circuit 5 k 5 k VCC 5 k 3 k 3 k 14 3 k 5 k GND 15 Timing Current Setting ITI 10 k 10 k VCC 5 k 20 pF 10 k 10 k 10 k 10 k 15 30 k GND 16 17 18 Wide-band RMS Timing Wide-band RMS Offset Absorption Variable Emphasis Offset Absorption WTI WRB dO Same as pin 13 Same as pin 14 VCC 10 k 10 k 20 k 50 k 18 3 k 6 pF 20 k 10 k GND Data Sheet S13417EJ2V0DS00 13 PC1851B (6/9) Pin No. 19 Pin Name Volume Control Offset Absorption Symbol VOL-C Internal Equivalent Circuit VCC 10 k 10 k 5 k 5 k 5 pF 5 k 5 k 25 k 20 k 10 k 10 k 10 k GND 19 20 21 22 VCA Offset Absorption Analog GND SDA (for I2C bus) Note VOA AGND SDA Same as pin 12 VCC 10 k 10 k 10 k 50 k 5 k 22 30 k 30 k GND 23 SCL (for I2C bus) Note SCL 10 k 10 k VCC 10 k 5 k 23 30 k 30 k GND 24 Digital GND (for I2C bus) DGND Note A protection diode on the VCC side is deleted not so as to pull the voltage of I2C bus line down to 0 V while the power supply is off (VCC = 0 V). 14 Data Sheet S13417EJ2V0DS00 PC1851B (7/9) Pin No. 25 Pin Name R-channel Output Symbol ROT 1 k 10 k Internal Equivalent Circuit VCC 200 25 200 5 k 1 k 5 k GND 26 27 L-channel Output Surround Timing LOT SUR Same as pin 25 VCC 27 24 k 20 k 40 k 2 k 20 k GND 28 R-channel Offset Absorption TRO VCC 35 k 5 k 35 k 5 k 28 40 k 10 k 10 k GND Data Sheet S13417EJ2V0DS00 15 PC1851B (8/9) Pin No. 29 Pin Name R-channel Capacity of High Frequency Band Width Symbol RTC Internal Equivalent Circuit VCC 36 k 5 k 36 k 5 k 29 40 k 10 k 10 k GND 30 R-channel Capacity of Low Frequency Band Width RBC 1 k 5 k 5 k VCC 30 5.3 k 3 k 2.5 k GND 31 32 L-channel Offset Absorption L-channel Capacity of High Frequency Band Width L-channel Capacity of Low Frequency Band Width R-channel Matrix Output L-channel Matrix Output TLO LTC Same as 28 Same as 29 33 LBC Same as 30 34 35 MOR MOL Same as 25 16 Data Sheet S13417EJ2V0DS00 PC1851B (9/9) Pin No. 36 Pin Name External R-channel Input 2 Symbol ER2 10 k 10 k Internal Equivalent Circuit 37 External L-channel Input 2 EL2 15 pF 40 k 36 40 k 38 External R-channel Input 1 ER1 10 k 39 External L-channel Input 1 EL1 I2C Bus 40 41 42 R-channel Fixed Output L-channel Fixed Output Monaural Offset Absorption FOR FOL MOA Same as pin 25 Same as pin 18 Data Sheet S13417EJ2V0DS00 17 PC1851B 2. BLOCK FUNCTIONS 2.1 Stereo Demodulation Block (1) Stereo LPF This filter eliminates signals in the vicinity of 5 fH to 6 fH, such as SAP (Sub Audio Program) (5 fH) and telemetry signals (6.5 fH) . The PC1851B's internal L-R demodulator, which uses a double-balanced circuit, demodulates L-R signals by multiplication of the L-R signal with the signal at the L-R carrier frequency (2 fH). The L-R signal tends to receive interference from the 6 fH signal because a square waveform is used as the switching carrier in this method. To eliminate this interference, the PC1851B incorporates traps at 5 fH and 6 fH. The filter response is adjusted by setting the FILTER SETTING bits (Write register, subaddress 02H, bits D0 to D5). (2) Stereo Phase Comparator The 8 fH signal generated at the Stereo VCO is divided by 8 (4 x 2) and then multiplied by the pilot signal passed through the stereo LPF. The two signals differ from each other by 90 degrees in terms of phase. The resistor and capacitor connected to the D1 and D2 pins form a filter that smoothes the phase error signal output from the Stereo Phase Comparator, converting the error signal to the DC voltage. When the voltage difference between D1 and D2 pins becomes 0 V (strictly speaking, not 0 V by the internal offset voltage), the VCO runs at 8 fH. The lag/lead filter externally connected to the pins D1 and D2 determines the capture range. (3) Stereo VCO The Stereo VCO runs at 8 fH with the internal capacitor. The frequency is adjusted by setting the STEREO VCO SETTING bits (Write register, subaddress 01H, bits D0 to D5). (4) Divider (Flip-flop) Produces two separate fH signals: the inphase fH signal, and the fH signal differing by 90 degrees from the input pilot signal by dividing the 8 fH frequency from the Stereo VCO by 8 (4 x 2). (5) Pilot Discrimination Phase Comparator (Level detector) Multiplies the pilot signal from the COM pin with the inphase fH signal from the divider. The resulting signal is smoothed by passing it through the external filter connected to the PD1 and PD2 pins and converted into DC voltage that is used to determine whether or not a stereo pilot is present (Read register, bit D6). (6) Pilot Canceler The fH signal from the divider is added to the stereo signal matrix depending on the level of the input pilot signal to cancel the pilot signal. (7) L+R LPF This LPF which has traps at fH and 24 kHz, allows only the monaural signal to pass through. The filter response is adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5). (8) De-emphasis The 75-s de-emphasis filter is for the monaural signal. The response is adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5). (9) L-R AM Demodulator Demodulates the L-R AM-DSB modulated signal by multiplying with the 2-fH signal which is synchronized to the pilot signal. The 2-fH square wave is used as the switching carrier. 18 Data Sheet S13417EJ2V0DS00 PC1851B 2.2 SAP Demodulation Block (1) SAP BPF Picks up the SAP signal by the 50-kHz and 102-kHz traps and a response peak at 5 fH. The filter response is adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5). (2) Noise BPF . The PC1851B monitors signals picked up by the noise BPF (fO =. 180 kHz), and distinguishes noise from signals. By this method, the PC1851B prevents faulty SAP detection in a weak electric field. The filter response is adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5). (3) Noise Detector Performs full-wave rectification of noise from noise BPF, changes it to the DC voltage, and inputs it to the comparator. When the noise level exceeds the reference level, the Noise detection bit (Read register, bit D4) turns "1". The sensitivity and time constant of the circuit are adjusted by setting the values of the resistor and capacitor connected to the NDT pin. (4) SAP Detector Detects the signal from the SAP BPF and smoothes it through the SDT pin and inputs it to the comparator. When it detects the SAP signal, the SAP broadcast (Broadcast status) (Read register, bit D5) turns "1". (5) SAP Demodulator The SAP demodulator consists of a phase detector, a loop filter and an SAP VCO (PLL detection circuit). The SAP VCO oscillates at 10 fH, and performs phase comparison between the signal divided by 2 of the SAP VCO frequency and the SAP signal to make the PLL. The SAP VCO oscillating frequency is adjusted by setting the SAP VCO SETTING bit (Write register, subaddress 05H, bits D0 to D5). (6) SAP LPF Eliminates the SAP carrier and high-frequency buzz. The filter consists of a 2nd-order LPF and fH trap filter. The filter response is adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5). Data Sheet S13417EJ2V0DS00 19 PC1851B 2.3 dbx Noise Reduction Block All the filters required for TV-dbx Noise Reduction are incorporated. These filter responses are adjusted by setting all the FILTER SETTING bits (Write register, subaddress 02H, bits D0 to D5). (1) LPF This LPF has traps at fH and 24 kHz each. The fH trap filter minimizes interference by the fH signal which is not synchronized with the pilot signal (for example, leakage of the synchronous idle and buzz from the video signal). (2) 408-Hz LPF This filter is a de-emphasis filter. Its transfer function is as follows: 1+j T(f) = 1+j f 5.23k f 408 (3) Variable Emphasis It is also called the spectral VCA. It is controlled by the spectral RMS. The transfer function is as follows: 1+j S -1 (f, b) = 1+j f 20.1k f 20.1k x x 1 + 51b b+1 1 + 51 b+1 where "b" is the variable transferred from the spectral RMS for controlling. (4) Wide-band VCA A VCA whose operating frequency range is mainly low to mid frequencies and controlled by the wide-band RMS. The transfer function is as follows: W -1 (a) = a where "a" is the variable transferred from the wide-band RMS for controlling. (5) 2.19-kHz LPF This filter is a de-emphasis filter. Its transfer function is as follows: 1+j T(f) = 1+j f 62.5k f 2.19k (6) Spectral RMS Filter A filter that limits the band width of the signal input to the RMS which controls the variable emphasis. The transfer function is as follows: f f )2 j 7.66k 3.92k x f f f 1+j +(j )2 1+j 7.31k 7.66k 3.92k (j T (f) = 20 Data Sheet S13417EJ2V0DS00 PC1851B (7) Wide-band RMS Filter A filter that limits the band width of the signal input to the wide-band RMS which controls the wide-band VCA. The transfer function is as follows: T(f) = 1+j 1 f 2.09k (8) Spectral RMS Detects the RMS value of the signal passed through the spectral RMS filter, and converts the signal to the DC voltage. The release time is set by adjusting the current IT of the PC1851B and the capacitance of the external capacitor connected to the STI pin. The current IT is adjusted by adjusting the current from the ITI pin. (9) Wide-band RMS Detects the RMS value of the signal passed through the wide-band RMS filter, and converts the signal to the DC voltage. The release time is set by adjusting the current IT of the PC1851B and the capacitance of the external capacitor connected to the WTI pin. The current IT is adjusted by adjusting the current from the ITI pin. 2.4 Matrix Block (1) Matrix Adds L+R signal and L-R signal to output L signal, and substracts L+R signal from L-R signal to output R signal. (2) Mode Selector The matrix block selects the signal from the monaural signal, Stereo signal, SAP signal by the User Mode. 2.5 Selector Block It selects the signal from the TV signal (signal with the audio multiple signal processed in the PC1851B) and external input (signal input from EL1, EL2, ER1 and ER2 pins), and outputs it to the surround processor block (surround, tone control, and volume control block). It also selects the gain of the selection signal (0 dB/6 dB) as well as switches the stereo/monaural output (by the I2C bus). Data Sheet S13417EJ2V0DS00 21 PC1851B 3. I2C BUS INTERFACE The PC1851B uses a 2-wire serial bus developed by Philips. The serial clock line (SCL) and serial data line (SDA) employ the 2-wire configuration as shown in Figure 3-1. The PC1851B contains an I2C bus interface circuit, eleven (8-bit) read/write registers, and one read-only register. Serial Clock Line (SCL) The master CPU outputs a serial clock to achieve data synchronicity. The PC1851B receives serial data based on this clock. The input level is CMOS-compatible. The clock frequency is from 0 to 100 kHz. Serial Data Line (SDA) The master CPU outputs data synchronously with the serial clock. The PC1851B receives this data based on the serial clock. The input level is CMOS-compatible Figure 3-1. Internal Equivalent Circuit of Interface Pins RP SCL SDA RP PC1851B For SCL and SDA pins, a protection diode on the VCC side is deleted not so as to pull the voltage of I2C bus line down to 0 V while the power supply is off (VCC = 0 V). 22 Data Sheet S13417EJ2V0DS00 PC1851B 3.1 Data Transfer (1) Start condition The start condition is created when SDA changes from high to low while SCL is high, as shown in Figure 3-2. When the PC1851B receives this information, it captures data sent in synchronization with the clock. (2) Stop condition The stop condition is created when SDA changes from low to high while SCL is high, as shown in Figure 3-2. When the PC1851B receives this information, it stops receiving or outputting data. Figure 3-2. Data Transfer Start/Stop Condition 3.5 V SDA 1.5 V 4.0 s MIN. 3.5 V SCL 1.5 V 4.7 s MIN. Start (3) Data transfer Stop When transferring data, be sure to switch data only when SCL is low, as shown in Figure 3-3. When SCL is high, the data must not be changed. Figure 3-3. Data Transfer SDA Note 1 Note 2 SCL Note 3 Note 4 Notes 1. Data hold time: 300 ns MIN. 2. Data setup time: 250 ns MIN. 3. Interval when data must not be changed. 4. Interval when data can be changed. Data Sheet S13417EJ2V0DS00 23 PC1851B 3.2 Data Transfer Format An example of data transfer in the write mode is shown in Figure 3-4. Figure 3-4. Data Transfer Example in Write Mode SDA D6 D5 D4 D3 D2 D1 D0 Write mode D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Start Slave address Read/ Acknowwrite ledge Subaddress Acknowledge Data Acknow- Stop ledge Data consists of 8-bit units. This 8-bit data must always be followed by an acknowledge bit. Data transfer must be done on an MSB-first basis. The first byte after a start condition specifies the slave address. The slave address consists of 7 bits. Table 3-1 shows the slave addresses of the PC1851B. These slave addresses are registered by Philips. Table 3-1. Slave Addresses of PC1851B Slave address Mode Write Read 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 1 D6 D5 D4 D3 D2 D1 D0 Read/Write The bit following the slave address is the read/write bit specifying the direction of the data to be transferred. During the read operation, data is transferred from the PC1851B to the master CPU. During the write operation, data is transferred from the master CPU to the PC1851B. "0" and "1" are written to the READ/WRITE bit during the Write and Read modes, respectively. The byte following the slave address is the subaddress of the PC1851B in the write mode. The PC1851B has eleven subaddresses, SA0 to SAA, which are made up of 8 bits. Following the subaddress byte is the data to be set to the subaddress. 24 Data Sheet S13417EJ2V0DS00 PC1851B (1) 1-byte data transfer The format for 1-byte data transfer is the following: Start Slave address Write Acknow Acknow Subaddress mode -ledge -ledge Data Acknow Stop -ledge (2) Continuous data transfer The format when transferring multiple (7) bytes of data at one time by using the automatic increment function is the following: Start Slave address Write Acknow Acknow Subaddress mode -ledge -ledge Data1 Acknow -ledge Data2 Acknow -ledge Data7 Acknow Stop -ledge The master CPU transfers "00H" as subaddress SA0 following the start condition and slave address. After the subaddress SA0, the master CPU transfers the SA0 data, and continues with SA1, SA2,..., SAA data without transferring stop conditions in between. Finally, the stop condition is transferred and the transfer is completed. (3) Data read The PC1851B has one read register. The contents of this register can be read by the master CPU. The format when data is read is the following: Nonacknow Stop -ledge Start Slave address Read Acknow -ledge Data (4) Acknowledge In the case of the I2C bus, an acknowledge bit is added to the data as the 9th bit to determine whether data transfer was successful. The master CPU determines the success or failure of data transfer based on whether this acknowledge bit is a logical low or high. If the acknowledge interval is a logical low, this indicates that data transfer was successful. If it is a logical high, this indicates that data transfer was unsuccessful or that the slave side forcibly released the bus. Data Sheet S13417EJ2V0DS00 25 PC1851B (5) Automatic increment The PC1851B has the automatic increment function. The automatic increment is applied to the subaddresses 00H to 05H of the write register. The user can set ON/OFF the automatic increment of the subaddresses 06H to 0AH (refer to 4.1 Subaddress List). Automatic increment ON: The subaddress is automatically increased. Setting the slave address and subaddress once enables the data of the next subaddress to be transferred without actually setting it. Automatic increment OFF: The subaddress is fixed. The data of the fixed subaddress can be set time after time. The increment of the subaddresses 06H to 0AH is individually controlled by each automatic increment ON/OFF bit. For example, if the automatic increment function of the subaddress 06H is set to ON and that of the subaddress 07H set to OFF, the subaddress is to be automatically increased from 06H to 07H and then fixed to 07H. Though the automatic increment function of the subaddress 0AH is set to ON, the subaddress is not to be increased. After setting the data of 0AH (acknowledge bit: low level), if the next data is transferred, the acknowledge is to be in non-acknowledge state (acknowledge bit: high level) and the data transfer from the master CPU is aborted. 26 Data Sheet S13417EJ2V0DS00 PC1851B 4. I2C BUS COMMANDS 4.1 Subaddress List (1) Write register (command list) Bit MSB D7 LSB D6 D5 D4 D3 D2 D1 D0 Subaddress 00H 0 During noise detection Stereo/SAP output stop 0: SAP OFF 1: Stereo, SAP OFF fH monitor ON/OFF 0: OFF 1: ON Pilot canceler ON/OFF 0: ON 1: OFF Input level setting 01H 0 Stereo VCO setting 02H 0 Filter setting 03H 0 Input gain 0: 0 dB 1: 6 dB Surround 0: OFF 1: ON 5fH monitor ON/OFF 0: OFF 1: ON Input select 1 00: TV signal 01: External input 1 10: External input 2 11: Setting prohibited Automatic increment 0: OFF 1: ON Low-band separation setting 04H 0 High-band separation setting 05H 0 SAP VCO setting 06H Automatic increment 0: OFF 1: ON Input select 2 SAP1/SAP2 Stereo/SAP 0: Stereo switchNote switch 1: Monaural 0: SAP1 0: Stereo 1: SAP2 1: SAP Forced monaural 0: OFF 1: ON Mute 0: ON 1: OFF 07H 0 Volume control 08H 0 Automatic increment 0: OFF 1: ON Automatic increment 0: OFF 1: ON Automatic increment 0: OFF 1: ON Balance control 09H 0 Bass control 0AH 0 Treble control Data Sheet S13417EJ2V0DS00 27 PC1851B Note Output when SAP1 or SAP2 is selectd is as follows: L-channel output (LOT pin) SAP1 SAP2 Monaural (L+R) SAP R-channel output (ROT pin) SAP (2) Read register MSB D7 D6 D5 D4 D3 D2 Reception status Noise detection Stereo broadcast reception 0: Not available 1: Available SAP broadcast reception 0: Not available 1: Available D1 LSB D0 Broadcast status Power-on reset Stereo pilot SAP signal 1 1 1: Detect 0: Not available 1: Available 0: Not available 1: Available 0: Not available 1: Available 28 Data Sheet S13417EJ2V0DS00 PC1851B 4.2 Setting Procedure Precise adjustment of the dbx decoder is absolutely critical for optimum performance. Where possible, the adjustment should be performed after the PC1851B is mounted on the chassis and with the video system active. Set the data of write register as follows before the adjustment. Table 4-1. Default Setting of Write Register Bit Subaddress 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 (1) Input level setting (Write register, subaddress 00H, bits D5 to D0) <1> Write "1" to bit D0 (Mute: OFF) of subaddress 06H. <2> Input sine wave of 300 Hz, 150 mVrms to COM pin. <3> Set bits D5 to D0 (INPUT LEVEL SETTING bits) of subaddress 00H so that the output level of FOR pin is 500 mVrms (10 mVrms). (2) Stereo VCO setting (Write register, subaddress 01H, bits D6 to D0) Perform this adjustment with no signal applied. <1> Write "1" to bit D0 (Mute: OFF) of subaddress 06H. <2> Write "1" to bit D6 (fH monitor: ON) of subaddress 01H. <3> Connect frequency counter to FOR pin, and set bits D5 to D0 (STEREO VCO SETTING bits) of subaddress 01H so that frequency counter displays 15.73 kHz (0.1 kHz). <4> When setting is completed, write "0" to bit D6 (fH monitor: OFF) of subaddress 01H. Data Sheet S13417EJ2V0DS00 29 PC1851B (3) Filter setting (Write register, subaddress 02H, bits D6 to D0) <1> Write "1" to bit D6 (Pilot canceler: OFF) of subaddress 02H. <2> Input pilot signal (15.734 kHz, 30 mVrms or higher Note) to COM pin and set data of bits D5 to D0 (FILTER SETTING bits) of subaddress 02H so that the AC output level of the FOR pin becomes as small as possible (Decrease the set data from 63 (decimal)). <3> When setting is completed, write "0" to bit D6 (pilot canceler: ON) of subaddress 02H. Note Recommended 100 mVrms. (4) Separation setting (Write register, subaddresses 03H and 04H, bits D5 to D0) <1> Write "1" to bit D0 (Mute: OFF) of subaddress 06H. <2> Write "20H" to bits D5 to D0 (HIGH-BAND SEPARATION SETTING bits) of subaddress 04H. <3> Input composite signal to COM pin (300 Hz, 30 % modulation, L-only, with noise reduction), and set bits D5 to D0 (LOW-BAND SEPARATION SETTING bits) of subaddress 03H so that the output level of the FOR pin is as small as possible. <4> Change the modulation frequency of the composite signal to 3 kHz, and set bits D5 to D0 of subaddress 04H so that the output level of the FOR pin is as small as possible. <5> While bits D5 to D0 of subaddress 04H are set as in step <4> above, repeat the setting procedure of step <3> for bits D5 to D0 of subaddress 03H. (5) SAP VCO setting (Write register, subaddress 05H, bits D6 to D0) Perform this adjustment with no signal applied. <1> Add a 1 M resistor between the SOA pin and GND. <2> Write "1" to bit D0 (Mute: OFF) of subaddress 06H. <3> Write "1" to bit D6 (5 fH monitor: ON) of subaddress 05H. <4> Connect a frequency counter to the FOR pin, and set bits D5 to D0 of subaddress 05H (SAP VCO SETTING bits) so that 78.67 kHz (0.5 kHz) is displayed on the frequency counter. <5> When setting is completed, write "0" to bit D6 (5 fH monitor: OFF) of subaddress 05H. <6> Delete the 1 M resistor between the SOA pin and GND. 30 Data Sheet S13417EJ2V0DS00 PC1851B 4.3 Explanation of Write Register (1) Stereo/SAP output stop function during noise detection Stereo/SAP output stop can be selected with the data of bit D6 of subaddress 00H during weak electrical field conditions (recommended noise level during circuit use is 34 mVrms (TYP.) or more). SAP output stop SAP and stereo output stop : Only SAP output is stopped. : SAP and stereo outputs are stopped, switch to monaural output. Noise level detection is performed, when detected a noise about at 11.5 fH (180 kHz), a frequency that is sufficiently apart from that of the high frequency signals such as the stereo, SAP, and telemetry signal. If noise is detected, "1" is set to bit D4 of the read register (Refer to section 4.4, (4) Noise detection) Figure 4-1. Stereo/SAP Output Stop Function During Noise Detection D7 00H 0 D6 During noise detection D5 D4 D3 D2 D1 D0 Input level setting Stereo/SAP output stop function during noise detection 0 1 SAP output stop SAP and stereo output stop (2) Mute The mute function can be set ON/OFF with the data of bit D0 of subaddress 06H. The mute on state is entered when bit D0 is set to 0 after power-on reset. Figure 4-2. Mute D7 06H Automatic increment D6 D5 D4 Input select 2 D3 SAP1/SAP2 switch D2 Stereo/SAP switch D1 Forced monaural ON/OFF D0 Mute ON/OFF Input select 1 Mute 0 Mute ON 1 Mute OFF Caution When switching the power ON/OFF, use the external mute (200 ms) in order to minimize shock noise. Data Sheet S13417EJ2V0DS00 31 PC1851B (3) Mode switch (L-, R-channel output (LOT, ROT pins)) The output signal for the L- and R-channel outputs (LOT, ROT pins) can be selected with bits D3 to D1 of subaddress 06H. For the combinations of data of each output signal bit, refer to 5. MODE MATRIX. Forced monaural ON/OFF : When set to ON, a monaural signal is forcibly output regardless of the selection of other bits. Stereo/SAP switch SAP1/SAP2 switch : When forced monaural is set to OFF, performs selection of stereo or SAP. : When SAP output is selected with the stereo/SAP switch, performs selection of SAP1 or SAP2. L-Channel Output (LOT pin) SAP1 SAP2 R-Channel Output (ROT pin) SAP output Monaural (L+R) output SAP output Figure 4-3. Mode Switch (L-, R-Channel Output (LOT, ROT pins)) D7 06H Automatic increment D6 D5 D4 Input select 2 D3 SAP1/SAP2 switch D2 Stereo/SAP switch D1 D0 Input select 1 Forced monaural Mute ON/OFF ON/OFF Forced monaural 0 Forced monaural OFF 1 Forced monaural ON Stereo/SAP switch 0 1 Stereo output SAP output SAP1/SAP2 switch 0 1 SAP1 output SAP2 output 32 Data Sheet S13417EJ2V0DS00 PC1851B (4) Input select The signal to be input to the selector block in the PC1851B can be selected by the data of bits D4 to D6 of subaddress 06H. The selected signal is output from the LOT, ROT, FOL and FOR pins. For the combination of bits for the signal to be selected, refer to 6. SELECTOR TABLE. Input select 1 : Input select 2 : switches the TV signal (signal with the audio multiple signal processed in the PC1851B) and external inputs 1 and 2 (signal input from EL1, EL2, ER1 and ER2 pins). switches the stereo signal and monaural signal. Figure 4-4. Input Select D7 06H Automatic increment D6 D5 D4 Input select 2 D3 SAP1/SAP2 switch D2 Stereo/SAP switch D1 Forced monaural ON/OFF D0 Mute Input select 1 Input select 2 L-channel output (LOT, FOL pins) 0 1 Note L-channel signal R-channel output (ROT, FOR pins) R-channel signal Monaural (L+R) signal Input select 1 00 01 10 11 TV signal External input 1 External input 2 Setting prohibited Note When SAP2 is selected by switching SAP1/SAP2, the L+R signal and SAP signal are composite to be output. Data Sheet S13417EJ2V0DS00 33 PC1851B (5) Input gain The gain of the signal to be input to the selector block in the PC1851B can be selected by the data of bit D6 of subaddress 03H. Figure 4-5. Input Gain D7 03H 0 D6 Input gain D5 D4 D3 D2 D1 D0 Low-band separation setting Input gain 0 1 0 dB 6 dB (6) Surround function The surround function ON/OFF can be selected by the data of bit D6 of subaddress 04H. Figure 4-6. Surround Function D7 04H 0 D6 Surround D5 D4 D3 D2 D1 D0 High-band separation setting Surround function 0 1 Surround OFF Surround ON 34 Data Sheet S13417EJ2V0DS00 PC1851B (7) Volume, Balance control The volume and balance of the output (LOT and ROT pins) can be controlled at 64 levels by the data of bits D0 to D5 of subaddresses 07H and 08H. The volume attenuation is 80 dB or higher. Figure 4-7. Volume, Balance Control * Volume control D7 07H 0 D6 Automatic increment D5 D4 D3 Volume control D2 D1 D0 Volume control Data D5 - D0 111111 | 000000 Attenuation volume Flat (0 dB) | Low * Balance control D7 08H 0 D6 Automatic increment D5 D4 D3 Balance control D2 D1 D0 Balance control Data D5 - D0 111111 | 100000 | 000000 Attenuation volume L-ch Low, R-ch Flat | TYP. | L-ch Flat, R-ch Low Data Sheet S13417EJ2V0DS00 35 PC1851B (8) Bass, Treble control The bass and treble sound quality of the output (LOT and ROT pins) can be controlled at 64 levels by the data of the bits D0 to D5 of subaddresses 09H and 0AH. The bass control amount of the low frequency band width boost/cut is 11 dB TYP. at 100 Hz. The treble control amount of the high frequency band width boost/cut is 13 dB TYP. at 10 kHz. Figure 4-8. Bass, Treble control * Bass control D7 09H 0 D6 Automatic increment D5 D4 D3 Bass control D2 D1 D0 Bass control Data Gain D5 - D0 111111 | 100000 | 000000 Boost | 0 dB | Cut * Treble control D7 0AH 0 D6 Automatic increment D5 D4 D3 Treble control D2 D1 D0 Treble control Data Gain D5 - D0 111111 | 100000 | 000000 Boost | 0 dB | Cut 36 Data Sheet S13417EJ2V0DS00 PC1851B (9) Automatic increment function The automatic increment function ON/OFF can be selected by the data of bit D7 of subaddress 06H and that of bit D6 of subaddresses 07H to 0AH. For the details of the automatic increment function, refer to 3.2 (5) Automatic increment. Figure 4-9. Automatic Increment Function D7 06H Automatic increment D6 D5 D4 Input select 2 D3 SAP1/SAP2 switch D2 Stereo/SAP switch D1 Forced monaural ON/OFF D0 Mute Input select 1 Automatic increment function 0 1 Automatic increment function OFF Automatic increment function ON Caution After power-on reset, be sure to set the data. Data Sheet S13417EJ2V0DS00 37 PC1851B 4.4 Explanation of Read Register (1) Power-on reset detection Whether a power-on reset was detected is detected with bit D7 of the read register. Figure 4-10. Power-On Reset Detection D7 Power-on reset Stereo broadcast SAP broadcast D6 D5 D4 D3 D2 D1 D0 Broadcast status Noise detection Reception status Stereo broadcast reception SAP broadcast reception 1 1 Power-on reset detection 1 Power-on reset detection (2) Stereo, SAP broadcast (broadcast status) detection Whether SAP or stereo broadcast from a broadcasting station is being broadcast is detected with bits D5 and D6 of the read register. When a SAP signal (5 fH) or stereo pilot signal is detected, the register data becomes "1". Figure 4-11. Stereo, SAP Broadcast (Broadcast Status) Detection D7 Power-on reset Stereo broadcast SAP broadcast D6 D5 D4 D3 D2 D1 D0 Broadcast status Noise detection Reception status Stereo broadcast reception SAP broadcast reception 1 1 SAP broadcast 0 1 No SAP broadcast SAP broadcast (SAP signal detected) Stereo broadcast 0 1 No Stereo broadcast Stereo broadcast (stereo pilot signal detected) 38 Data Sheet S13417EJ2V0DS00 PC1851B (3) Stereo, SAP broadcast reception (reception status) detection Whether SAP or stereo broadcast is being received and the PC1851B outputs the audio signal can be detected with bits D2 and D3 of the read register. The register data become "1" only if the SAP signal (5 fH) is detected when the SAP broadcast reception is selected, or if the stereo pilot signal is detected when the stereo broadcast reception is selected. Figure 4-12. Stereo, SAP Broadcast Reception (Reception Status) Detection D7 Power-on reset Stereo broadcast SAP broadcast D6 D5 D4 D3 D2 D1 D0 Broadcast status Noise detection Reception status Stereo broadcast reception SAP broadcast reception 1 1 SAP broadcast reception 0 1 No outputing SAP broadcast Outputing SAP broadcast Stereo broadcast reception 0 1 No outputing stereo broadcast Outputing stereo broadcast (4) Noise detection Noise can be detected with bit D4 of the read register. It is monitored in the vicinity of the 11.5 fH (180 kHz) signal level. During noise detection, the operation of the SAP demodulator block and the stereo demodulation block is interrupted (Refer to section 4.3 (1) Stereo/SAP output stop function during noise detection). Figure 4-13. Noise Detection D7 Power-on reset D6 D5 D4 D3 D2 D1 D0 Broadcast status Stereo broadcast SAP broadcast Noise detection Reception status Stereo broadcast reception SAP broadcast reception 1 1 Noise detection 0 1 No noise Noise Data Sheet S13417EJ2V0DS00 39 PC1851B 5. MODE MATRIX Mute OFF (Write register, subaddress 06H, bit D0 : "1") (1) Read register, bit D4: 0 Broadcast mode Forced monaural ON/OFF Write Register Stereo /SAP switch Subaddress 06H Bit D1 Monaural Stereo - 0 1 Monaural+SAP 0 0 1 - 0 1 1 Stereo+SAP 0 - 0 1 - - 0 1 1 - - L+R L+R - L SAP SAP 0 L+R L+R R 1 1 1 0 - Bit D2 - - Bit D3 - - SAP1 /SAP2 switch Stereo /SAP output stop Subaddress 00H Bit D6 - - L L+R L+R SAP SAP 0 0 1 0 1 L+R R Bit D6 0 1 Bit D5 0 0 Bit D3 0 1 0 0 0 1 Bit D2 0 0 Output L-ch output (LOT ) R-ch output (ROT) Read Register Broadcast status Stereo pilot SAP signal Reception status Stereo SAP broadcast broadcast reception reception (2) Read register, bit D4: 1 Output Stereo /SAP output stop Subaddress 00H Bit D3 - - Bit D6 - 0 1 L L+R L+R L+R R Bit D6 0 1 0 0 0 Bit D5 0 0 Bit D3 0 1 0 0 0 Bit D2 0 0 L-ch outputl (LOT) R-ch output (ROT) Read Register Broadcast status Stereo pilot SAP signal Reception status Stereo SAP broadcast broadcast reception reception Broadcast mode Forced monaural ON/OFF Write Register Stereo /SAP switch Subaddress 06H Bit D1 Bit D2 - - SAP1 /SAP2 switch Monaural Stereo - 0 Monaural+SAP 0 1 0 0 1 1 0 1 Stereo+SAP 0 0 - 0 1 L L+R R 1 0 0 1 0 0 1 0 0 1 1 0 1 Remarks 1. When the PC1851B recognizes a weak electric field, bit D4 of the read register becomes "1". 2. --: Don't care. 40 Data Sheet S13417EJ2V0DS00 PC1851B 6. SELECTOR TABLE Input signal: TV signal (signal with the audio multiple signal processed in the PC1851B) External input 1 (signal input from EL1, ER1 pins) External input 2 (signal input from EL2, ER2 pins) Write Register Mute ON/OFF Input select 1 Subaddress : 06H Bit : D0 0 1 Bits : D6, D5 -- 00 01 10 11 00 01 10 11 Remark - : Don't care 1 Bit : D4 - 0 TV signal (L) External input 1 (L) External input 2 (L) Mute TV signal (R) External input 1 (R) External input 2 (R) Input select 2 L-channel output (LOT, FOL pins) L-channel, R-channel L-channel, R-channel L-channel, R-channel Output R-channel output (ROT, FOR pins) Setting prohibited (no signal, unconnected) TV signal External input 1 External input 2 1 2 1 2 1 2 (L+R) (L+R) (L+R) Setting prohibited (no signal, unconnected) Data Sheet S13417EJ2V0DS00 41 PC1851B 7. USAGE CAUTIONS 7.1 Caution on Shock Noise Reduction When switching the power ON/OFF, use the external mute (approx. 200 ms) in order to minimize shock noise (Refer to section 4.3 (2) Mute). 7.2 Supply Voltage Pass data through the I2C bus only after stabilizing the supply voltage of the entire application system. 7.3 Impedance of Input and Output Pins Table 7-1. Impedance of Input and Output Pins Input pin Symbol COM SI EL1, EL2 ER1, ER2 Description Composite signal input SAP single input External L-channel input External R-channel input Impedance 80 k Symbol SOT ROT LOT MOR MOL FOR FOL Output pin Description SAP single input R-channel output L-channel output R-channel matrix output L-channel matrix output R-channel fixed output L-channel fixed output Impedance 360 15 7.4 Drive Capability of Output Pins Table 7-2. Drive Capability of Output Pins Pin symbol SOT ROT LOT MOR MOL FOR FOL Remark Pin description SAP single output R-channel output L-channel output R-channel matrix output L-channel matrix output R-channel fixed output L-channel fixed output If the load capacitance of the output pins (SOT, ROT, LOT, MOR, MOL, FOR, FOL pins) exceeds 100 pF, parasitic oscillation may occur. In this case, connect a resistor between the output pins and the load capacitance. Bear in mind that the load capacitance is changed by wiring pattern on the printed circuit board. Output pin-GND Connection Resistance 10 k Drive capability 3-k load or less 700- load or less 42 Data Sheet S13417EJ2V0DS00 PC1851B 7.5 Caution on External Components According to the license contract with THAT Corporation, use the following for external components. With regard to the use of other external components, please contact to THAT corporation. Table 7-3. External Components Pin symbol ITI STI WTI Pin description Timing current setting Spectral RMS timing Wide-band RMS timing External component Metal film resistor (1 %) Tantalum capacitor (10 %) 7.6 Change of Electrical Characteristics by External Components (1) SAP sensitivity can be lowered by inserting a resistor between the SDT pin and GND. (2) Noise sensitivity can be changed by changing the value of the resistor between the NDT pin and GND. (3) The capture range can be changed by changing the recommended 1 F value of the capacitor between the D1 and D2 pins. Reducing the capacitor value increases the capture range, and increasing it reduces the capture range. However, too small a capacitor value may cause the distortion rate to become worse during stereo output, or may cause malfunction. In this case, please contact NEC. Data Sheet S13417EJ2V0DS00 43 PC1851B 8. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (unless otherwise specified, TA = 25 C) Parameter Power supply voltage I2C bus input pin voltage Composite signal input voltage Package power dissipation Operating ambient temperature Storage temperature Symbol VCC Vcont Vin PD TA Tstg VCC = 9 V VCC pin SDA, SCL pins COM pin Conditions Ratings 11.0 VCC VCC 700 -20 to +75 -40 to +125 Unit V V V mW C C Caution Exposure to Absolute Maximum Rating for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. Recommended Operating Conditions (unless otherwise specified, TA = 25 C) Parameter Power supply voltage I2C bus input pin voltage (High level) I C bus input pin voltage (Low level) Input impedance Output load impedance 1 2 Symbol VCC Vcont(H) Vcont(L) Rin RL1 VCC pin SDA, SCL pins Conditions MIN. 8.0 3.5 0 TYP. 9.0 - - - - MAX. 10.0 5.0 1.5 95 - Unit V V V k k COM, SI, EL1, EL2, ER1, ER2 pins LOT, ROT, MOL, MOR, FOL, FOR pins, AC load impedance at 100 % modulation SOT pin, AC load impedance at 100 % modulation LOT, ROT, MOL, MOR, FOL, FOR pins, DC load impedance at 100 % modulation SOT pin, DC load impedance at 100 % modulation COM pin L+R signal, 100 % modulation L-R signal, 100 % modulation Pilot signal SAP signal 60 2.0 Output load impedance 2 RL2 10.0 - - k Output load impedance 3 RL3 5.0 - - k Output load impedance 4 RL4 25.0 - - k Composite signal input voltage Vin - - - - - - 0.424 0.848 0.0848 0.254 1.4 - - - - - 5.6 100 Vp-p Vp-p Vp-p Vp-p Vp-p kHz External input signal voltage Clock frequency Vext fSCL EL1, EL2, ER1, ER2 pins SCL pin 44 Data Sheet S13417EJ2V0DS00 PC1851B Electrical Characteristics (unless otherwise specified, TA = 25 C, RH 70 %, VCC = 9.0 V, adding 30 kHz LPF to output pins) (1/3) Parameter Input: COM pin, Output: FOL, FOR pins Supply current Stereo detection input sensitivity Stereo detection hysteresis Stereo detection capture range ICC STSENCE STHY STCCL STCCH SAP detection input sensitivity SAP detection hysteresis Noise detection input sensitivity SAPSENCE SAPHY NOSENCE No signal 15.734 kHz, sine wave Only stereo pilot signal input Vin = 30 mVrms Only stereo pilot signal input f = 78.67 kHz, 0% modulation Only SAP carrier input Input sine wave f: Noise BPF peak Input sine wave f: Noise BPF peak 300 Hz, 100% modulation, Pre-emphasis: ON 300 Hz, 100 % modulation Noise reduction: ON 300 Hz, 100% modulation - 11 5.0 -5.5 +2.5 17 3.3 20 57 16 5.7 -4.0 +4.0 23 4.8 30 75 21 10 -2.5 +5.5 30 6.3 40 mA mVrms dB % % mVrms dB mVrms Symbol Conditions MIN. TYP. MAX. Unit Noise detection hysteresis NOHY 1 2 3 dB Monaural total output voltage VOMO 480 500 520 mVrm Stereo total output voltage SAP total output voltage Difference between monaural L and R output voltage Monaural total frequency characteristics 1 VOST VOSAP1 VOLR 450 400 -0.5 500 500 - 550 600 +0.5 mVrms mVrms dB VOMO1 1 kHz, 30% modulation, (f = 300 Hz: 0 dB) Pre-emphasis: ON 3 kHz, 30% modulation, (f = 300 Hz: 0 dB) Pre-emphasis: ON 8 kHz, 30% modulation, (f = 300 Hz: 0 dB) Pre-emphasis: ON 12 kHz, 30% modulation, (f = 300 Hz: 0 dB) Pre-emphasis: ON 1 kHz, 30% modulation, (f = 300 Hz: 0 dB) Noise reduction: ON -0.5 - +0.5 dB Monaural total frequency characteristics 2 VOMO2 -0.5 - +0.5 dB Monaural total frequency characteristics 3 VOMO3 -0.8 - +0.8 dB Monaural total frequency characteristics 4 VOMO4 -5.5 -3.0 -1.5 dB Stereo total frequency characteristics 1 VOST1 -0.5 - +0.5 dB Stereo total frequency characteristics 2 VOST2 3 kHz, 30% modulation, (f = 300 Hz: 0 dB) Noise reduction: ON 8 kHz, 30% modulation, (f = 300 Hz: 0 dB) Noise reduction: ON 12 kHz, 30% modulation, (f = 300 Hz: 0 dB) Noise reduction: ON 1 kHz, 30% modulation, (f = 300 Hz: 0 dB) Noise reduction: ON 3 kHz, 30% modulation, (f = 300 Hz: 0 dB) Noise reduction: ON 8 kHz, 30% modulation, (f = 300 Hz: 0 dB) Noise reduction: ON 300 Hz, 30% modulation -0.5 - +0.5 dB Stereo total frequency characteristics 3 VOST3 -1.0 - +1.0 dB Stereo total frequency characteristics 4 VOST4 -8.0 -5.0 -2.0 dB SAP total frequency characteristics 1 VOSAP11 -1.2 +0.3 +1.2 dB SAP total frequency characteristics 2 VOSAP12 -1.2 0.0 +1.2 dB SAP total frequency characteristics 3 VOSAP13 -4.0 -1.0 +1.0 dB Stereo channel separation 1 Sep1 27 32 - dB Data Sheet S13417EJ2V0DS00 45 PC1851B (2/3) Parameter Stereo channel separation 2 Stereo channel separation 3 Stereo channel separation 4 Stereo channel separation 5 Monaural total harmonic distortion Symbol Sep2 Sep3 Sep4 Sep5 THDMO Conditions 1 kHz, 30% modulation 3 kHz, 30% modulation 5 kHz, 30 % modulation 8 kHz, 30 % modulation 1 kHz, 100% modulation Pre-emphasis: ON 1 kHz, 100% modulation Noise reduction: ON 8 kHz, 30% modulation Noise reduction: ON 1 kHz, 100% modulation Noise reduction: ON SAP : 1 kHz, 100 % modulation Stereo : Pilot signal only, 0 % modulation Filter: 1 kHz BPF User mode: Stereo Stereo : 1 kHz, 100 % modulation, SAP : Carrier only, 0 % modulation Filter: 1 kHz BPF User mode: SAP1 300 Hz, 100% modulation Pre-emphasis: ON 300 Hz, 100 % modulation Noise reduction: ON MIN. 23 27 23 - - TYP. 30 35 30 25 0.1 MAX. - - - - 0.5 Unit dB dB dB dB % Stereo total harmonic distortion 1 THDST1 - 0.3 1.5 % Stereo total harmonic distortion 2 THDST2 - 0.8 1.8 % SAP total harmonic distortion Crosstalk 1 (SAP Stereo) THDSAP - 0.5 2.0 % CT1 - - -65 dB Crosstalk 2 (Stereo SAP) CT2 - - -65 dB Monaural total S/N S/NMO 65 68 - dB Stereo total S/N SAP total S/N S/NST S/NSAP 60 70 65 80 - - dB dB Input: External input pins, output: LOT, ROT pins Total muting level Mute TV signal : 1 kHz, 100 % modulation External input : 1 kHz, 500 mVrms Current provided to STI and WTI pins Mute Monaural Mute Stereo Mute SAP1 Mute External input External L-channel input : 100 Hz, 150 mVrms Surround : ON, LOT pin External L-channel input : 1 kHz, 150 mVrms Surround : ON, LOT pin External L-channel input : 10 kHz, 150 mVrms Surround : ON, LOT pin External L-channel input : 1 kHz, 150 mVrms Surround : ON, ROT pin 80 - - dB Timing current Inter-mode DC offset 1 Inter-mode DC offset 2 Inter-mode DC offset 3 Inter-mode DC offset 4 Surround output characteristics 1 IT VDOF1 VDOF2 VDOF3 VDOF4 VSR1L 7.1 -50 -50 -50 -50 -7.5 7.5 - - - - -4.5 7.9 +50 +50 +50 +50 0.0 A mV mV mV mV dB Surround output characteristics 2 VSR2L 4.0 5.6 7.0 dB Surround output characteristics 3 VSR3L 4.5 - 8.0 dB Surround output characteristics 4 VSR4R -1.5 - +1.5 dB 46 Data Sheet S13417EJ2V0DS00 PC1851B (3/3) Parameter Symbol Conditions Subaddress 09H Data MIN. TYP. MAX. Unit Low frequency band width boost control Low frequency band width cut control High frequency band width boost control High frequency band width cut control Volume attenuation 1 Volume attenuation 2 Volume attenuation 3 Balance attenuation L-ch 1 Balance attenuation L-ch 2 Balance attenuation L-ch 3 Balance attenuation L-ch 4 Balance attenuation R-ch 1 Balance attenuation R-ch 2 Balance attenuation R-ch 3 Balance attenuation R-ch 4 Difference between monaural L and R output voltage 1 (in case of external input) Difference between monaural L and R output voltage 2 (in case of external input) Difference between monaural L and R output voltage 3 (in case of external input) Crosstalk 3 TV signal External input Crosstalk 4 L-ch R-ch Total harmonic distortion (in case of external input) Maximum input voltage of external input VBB VBC VTB VTC ATTVL1 ATTVL2 ATTVL3 ATTBL1 ATTBL2 ATTBL3 ATTBL4 ATTBR1 ATTBR2 ATTBR3 ATTBR4 VOLR1 100 Hz, External input = 150 mVrms 10 kHz, External input = 150 mVrms 1 kHz, External input = 500 mVrms 3FH 00H 9 -13 10 -16 -1.0 -20 - - -14 -1.0 -1.0 -1.0 -1.0 -14 - -1.5 11 -11 13 -13 0.0 -17.5 - - -10 0.0 0.0 0.0 0.0 -10 - 0.0 13 -9 16 -10 +1.0 -14 -80 -60 -6 +1.0 +1.0 +1.0 +1.0 -6 -60 +1.5 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 0AH 3FH 00H 07H 3FH 20H 00H 1 kHz, External input = 500 mVrms 08H 3FH 30H 20H 00H 3FH 20H 10H 00H 1 kHz, External input = 500 mVrms 07H 3FH VOLR2 20H -2.0 0.0 +2.0 dB VOLR3 10H -3.0 0.0 +3.0 dB CT3 TV signal: 1 kHz, 100 % modulation External input: 1 kHz, 500 mVrms 1 kHz, External input = 500 mVrms 1 kHz, Total harmonic distortion rate: 1 % (External input) No signal, Rg = 600 , Filter: DIN/AUDIO 07H 3FH - - -80 dB CT4 - -80 -70 dB THDEXT 07H 3FH - 0.1 0.5 % VIEM 07H 3FH 1.7 2.1 - Vrms Output noise (in case of external input) NO 07H 3FH - 50 150 Vrms Data Sheet S13417EJ2V0DS00 47 PC1851B Test Condition Parameters for Electrical Characteristics (Unless otherwise specified, TA = 25 C, RH 70 %, VCC = 9 V, adding 30 kHz LPF to output pins) (1/8) Parameter Supply current Stereo detection input sensitivity Stereo detection hysteresis Symbol ICC STSENCE Test Conditions ICC : Current sent to VCC pin when there is no signal STSENCE : Input signal level of COM pin (input signal: 15.734 kHz) When read register D6 changes from 0 to 1 STHY =20 log (STSENCE / V) STSENCE: Stereo detection input sensitivity V: Input signal level of COM pin (Input signal: 15.734 kHz) Read register D6 is first set to 1, then input signal level is gradually lowered until D6 is changed to 0 STCCL = f / 15.734 kHz f: Difference between f and 15.734 kHz f: Input signal (14.5 kHz, 30 mVrms) to COM pin. Gradually raise frequency and measure frequency when read register D6 becomes 1. STCCH STCCH = f / 15.734 kHz f: Difference between f and 15.734 kHz f: Input signal (17.0 kHz, 30 mVrms) to COM pin. Gradually lower frequency and measure frequency when read register D6 becomes 1. SAPSENCE : Input signal level of COM pin (input signal: 78.67 kHz) When read register D5 changes from 0 to 1 SAPHY =20 log (SAPSENCE / V) SAPSENCE: SAP detection input sensitivity V: Input signal level of COM pin (Input signal: 78.67 kHz) When read register D5 is first set to 1, input signal level is gradually lowered until D5 becomes 0. NOSENCE: Input signal level of COM pin Read register D4: Apply 6-V DC voltage to SDT pin to change it to 0 Read register D4: Input signal (160 kHz, 10 mVrms) to COM pin. Raise the frequency until the DC voltage of the NDT pin reaches the maximum level, and then, while maintaining the frequency level, gradually raise the input signal level until D4 becomes 1. NOHY = 20 log (NOSENCE / V) NOSENCE: Noise detection input sensitivity V: Input signal level of NDT pin COM pin: Signal (160 kHz, 10 mVrms) input After read register D4 is set to 1, raise the frequency until the DC voltage of the NDT pin reaches the maximum level, and then, while maintaining the frequency level, gradually lower the input signal level until D4 becomes 0. VOMO : Output voltage of FOL and FOR pins COM pin: Monaural signal (300 Hz, 100 % modulation) input L-channel VOST : Output voltage of FOL pin COM pin: Stereo signal (L-only, 300 Hz, 100 % modulation) input R-channel VOST : Output voltage of FOR pin COM pin: Stereo signal (R-only, 300 Hz, 100 % modulation) input Monaural SAP SAP User Mode Note Monaural Stereo STHY Stereo detection capture range STCCL SAP detection input sensitivity SAP detection hysteresis SAPSENCE SAPHY Noise detection input sensitivity NOSENCE Noise detection hysteresis NOHY Monaural total output voltage VOMO Stereo total output voltage VOST Stereo Note For details about the User Mode, refer to 5. MODE MATRIX. 48 Data Sheet S13417EJ2V0DS00 PC1851B (2/8) Parameter SAP total output voltage Symbol VOSAP1 Test Conditions VOSAP1 : Output voltage of FOL and FOR pins COM pin: SAP signal (300 Hz, 100 % modulation) input VOLR = 20 log (VL / VR) VL: Output voltage of FOL pin COM pin: Monaural signal (300 Hz, 100 % modulation) input VR: Output voltage of FOR pin COM pin: Monaural signal (300 Hz, 100 % modulation) input VOMO1 = 20 log {V(1k) / V(300)} V(1k): Output voltage of FOL pin COM pin: Monaural signal (1 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: Monaural signal (300 Hz, 30 % modulation) input VOMO2 = 20 log {V(3k) / V(300)} V(3k): Output voltage of FOL pin COM pin: Monaural signal (3 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: Monaural signal (300 Hz, 30 % modulation) input VOMO3 = 20 log {V(8k) / V(300)} V(8k): Output voltage of FOL pin COM pin: Monaural signal (8 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: Monaural signal (300 Hz, 30 % modulation) input VOMO4 = 20 log {V(12k) / V(300)} V(12k): Output voltage of FOL pin COM pin: Monaural signal (12 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: Monaural signal (300 Hz, 30 % modulation) input VOST1 = 20 log {V(1k) / V(300)} V(1k): Output voltage of FOL pin COM pin: Stereo signal (L-only, 1 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: Stereo signal (L-only, 300 Hz, 30 % modulation) input VOST2 = 20 log {V(3k) / V(300)} V(3k): Output voltage of FOL pin COM pin: Stereo signal (L-only, 3 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: Stereo signal (L-only, 300 Hz, 30 % modulation) input VOST3 = 20 log {V(8k) / V(300)} V(8k): Output voltage of FOL pin COM pin: Stereo signal (L-only, 8 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: Stereo signal (L-only, 300 Hz, 30 % modulation) input VOST4 = 20 log {V(12k) / V(300)} V(12k): Output voltage of FOL pin COM pin: Stereo signal (L-only, 12 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: Stereo signal (L-only, 300 Hz, 30 % modulation) input Stereo User Mode Note SAP1 Difference between monaural L and R output voltage VOLR Monaural Monaural total frequency characteristics 1 VOMO1 Monaural Monaural total frequency characteristics 2 VOMO2 Monaural total frequency characteristics 3 VOMO3 Monaural total frequency characteristics 4 VOMO4 Stereo total frequency characteristics 1 VOST1 Stereo total frequency characteristics 2 VOST2 Stereo total frequency characteristics 3 VOST3 Stereo total frequency characteristics 4 VOST4 Note For details about the User Mode, refer to 5. MODE MATRIX. Data Sheet S13417EJ2V0DS00 49 PC1851B (3/8) Parameter SAP total frequency characteristics 1 Symbol VOSAP11 Test Conditions VOSAP11 = 20 log {V(1k) / V(300)} V(1k): Output voltage of FOL pin COM pin: SAP signal (1 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: SAP signal (300 Hz, 30 % modulation) input VOSAP12 = 20 log {V(3k) / V(300)} V(3k): Output voltage of FOL pin COM pin: SAP signal (3 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: SAP signal (300 Hz, 30 % modulation) input VOSAP13 = 20 log {V(8k) / V(300)} V(8k): Output voltage of FOL pin COM pin: SAP signal (8 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: SAP signal (300 Hz, 30 % modulation) input L-channel Sep1 = 20 log (VL / VR) VL: Output voltage of FOL pin COM pin: Stereo signal (L-only, 300 Hz, 30% modulation) input VR: Output voltage of FOR pin COM pin: Stereo signal (L-only, 300 Hz, 30 % modulation) input R-channel Sep1 = 20 log (VR / VL) VR: Output voltage of FOR pin COM pin: Stereo signal (R-only, 300 Hz, 30 % modulation) input VL: Output voltage of FOL pin COM pin: Stereo signal (R-only, 300 Hz, 30 % modulation) input Stereo channel separation 2 Sep2 L-channel Sep2 = 20 log (VL / VR) VL: Output voltage of FOL pin COM pin: Stereo signal (L-only, 1 kHz, 30 % modulation) input VR: Output voltage of FOR pin COM pin: Stereo signal (L-only, 1 kHz, 30 % modulation) input R-channel Sep2 = 20 log (VR / VL) VR: Output voltage of FOR pin COM pin: Stereo signal (R-only, 1 kHz, 30 % modulation) input VL: Output voltage of FOL pin COM pin: Stereo signal (R-only, 1 kHz, 30 % modulation) input Stereo channel separation 3 Sep3 L-channel Sep3 = 20 log (VL / VR) VL: Output voltage of FOL pin COM pin: Stereo signal (L-only, 3 kHz, 30 % modulation) input VR: Output voltage of FOR pin COM pin: Stereo signal (L-only, 3 kHz, 30 % modulation) input R-channel Sep3 = 20 log (VR / VL) VR: Output voltage of FOR pin COM pin: Stereo signal (R-only, 3 kHz, 30 % modulation) input VL: Output voltage of FOL pin COM pin: Stereo signal (R-only, 3 kHz, 30 % modulation) input Stereo User Mode Note SAP1 SAP total frequency characteristics 2 VOSAP12 SAP total frequency characteristics 3 VOSAP13 Stereo channel separation 1 Sep1 Note For details about the User Mode, refer to 5. MODE MATRIX. 50 Data Sheet S13417EJ2V0DS00 PC1851B (4/8) Parameter Stereo channel separation 4 Symbol Sep4 Test Conditions L-channel Sep4 = 20 log (VL / VR) VL: Output voltage of FOL pin COM pin: Stereo signal (L-only, 5 kHz, 30 % modulation) input VR: Output voltage of FOR pin COM pin: Stereo signal (L-only, 5 kHz, 30 % modulation) input R-channel Sep4 = 20 log (VR / VL) VR: Output voltage of FOR pin COM pin: Stereo signal (R-only, 5 kHz, 30 % modulation) input VL: Output voltage of FOL pin COM pin: Stereo signal (R-only, 5 kHz, 30 % modulation) input Stereo channel separation 5 Sep5 L-channel Sep5 = 20 log (VL / VR) VL: Output voltage of FOL pin COM pin: Stereo signal (L-only, 8 kHz, 30 % modulation) input VR: Output voltage of FOR pin COM pin: Stereo signal (L-only, 8 kHz, 30 % modulation) input R-channel Sep5 = 20 log (VR / VL) VR: Output voltage of FOR pin COM pin: Stereo signal (R-only, 8 kHz, 30 % modulation) input VL: Output voltage of FOL pin COM pin: Stereo signal (R-only, 8 kHz, 30 % modulation) input Monaural total harmonic distortion Stereo total harmonic distortion 1 THDMO THDMO : Distortion rate of FOL and FOR pins COM pin: Monaural signal (1 kHz, 100 % modulation) input L-channel THDST1 : Distortion rate of FOL pin COM pin: Stereo signal (L-only, 1 kHz, 100 % modulation) input R-channel THDST1 : Distortion rate of FOR pin COM pin: Stereo signal (R-only, 1 kHz, 100 % modulation) input Stereo total harmonic distortion 2 THDST2 L-channel THDST2 : Distortion rate of FOL pin COM pin: Stereo signal (L-only, 8 kHz, 30 % modulation) input R-channel THDST2 : Distortion rate of FOR pin COM pin: Stereo signal (R-only, 8 kHz, 30 % modulation) input SAP total harmonic distortion Crosstalk 1 (SAPStereo) CT1 THDSAP THDSAP : Distortion rate of FOL and FOR pins COM pin: SAP signal (1 kHz, 100 % modulation) input CT1 = 20 log (VCT1 / 500 mV) VCT1: Measure output voltage of FOL or FOR pins after BPF (1 kHz) SAP: 1 kHz, 100 % modulation Stereo: Pilot signal only, 0 % modulation CT2 = 20 log (VCT2 / 500 mV) VCT2: Measure output voltage of FOL or FOR pins after BPF (1 kHz) Stereo: 1 kHz, 100 % modulation SAP: Carrier only, 0 % modulation SAP1 Monaural User Mode Note Stereo THDST1 Stereo Stereo Crosstalk 2 (StereoSAP) CT2 SAP1 Note For details about the User Mode, refer to 5. MODE MATRIX. Data Sheet S13417EJ2V0DS00 51 PC1851B (5/8) Parameter Monaural total S/N Symbol S/NMO Test Conditions L-channel S/NMO = 20 log (VOMOL / VL) VOMOL : Output voltage of FOL pin after LPF (30 kHz) COM pin: Monaural signal (300 Hz, 100 % modulation) input VL: Output voltage of FOL pin (no signal) R-channel S/NMO = 20 log (VOMOR / VR) VOMOR: Output voltage of FOR pin after LPF (30 kHz) COM pin: Monaural signal (300 Hz, 100 % modulation) input VR: Output voltage of FOR pin (no signal) Stereo total S/N S/NST L-channel S/NST = 20 log (VOSTL / VL) VOSTL : Output voltage of FOL pin after LPF (30 kHz) COM pin: Stereo signal (L-only, 300 Hz, 100 % modulation) input VL: Output voltage of FOL pin COM pin: Pilot signal input R-channel S/NST = 20 log (VOSTR / VR) VOSTR : Output voltage of FOR pin after LPF (30 kHz) COM pin: Stereo signal (R-only, 300 Hz, 100 % modulation) input VR: Output voltage of FOR pin COM pin: Pilot signal input SAP total S/N S/NSAP L-channel S/NSAP = 20 log (VOSAP1L / VL) VOSAP1L : Output voltage of FOL pin after LPF (30 kHz) COM pin: SAP signal (300 Hz, 100 % modulation) input VL: Output voltage of FOL pin COM pin: SAP carrier (0 % modulation) input R-channel S/NSAP = 20 log (VOSAP1R / VR) VOSAP1R : Output voltage of FOR pin after LPF (30 kHz) COM pin: SAP signal (300 Hz, 100 % modulation) input VR: Output voltage of FOR pin COM pin: SAP carrier (0 % modulation) input Total muting level Mute Mute = 20 log (VOMOL / VM) VOMOL : Output voltage of LOT pin COM pin: Monaural signal (1 kHz, 100 % modulation) input VM : Output voltage of LOT pin Write register 06H, D0: 0 COM pin: Monaural signal (1 kHz, 100 % modulation) input IT : Current that flows from VCC to STI, WTI pins STI, WTI pins : 6 V DC is applied. VDOF1 = VMONO - VMute VMONO : DC voltage at LOT and ROT pins User mode : Monaural NDT pin: 6 V DC is applied. VMute : DC voltage at LOT and ROT pins User mode : Mute (write register 06H, D1: 0) NDT pin: 6 V DC is applied. Mute to Monaural Monaural mute SAP1 Stereo User Mode Note Monaural Timing current IT Inter-mode DC offset 1 VDOF1 Note For details about the User Mode, refer to 5. MODE MATRIX. 52 Data Sheet S13417EJ2V0DS00 PC1851B (6/8) Parameter Inter-mode DC offset 2 Symbol VDOF2 Test Conditions VDOF2 = VST - VMute VST : DC voltage at LOT and ROT pins User mode : Stereo NDT pin: 6 V DC is applied. VMute : DC voltage at LOT and ROT pins User mode : Mute (write register 06H, D1: 0) NDT pin: 6 V DC is applied. VDOF3 = VSAP - VMute VSAP : DC voltage at LOT and ROT pins User mode : SAP1 NDT pin: 6 V DC is applied. VMute : DC voltage at LOT and ROT pins User mode : Mute (write register 06H, D1: 0) NDT pin: 6 V DC is applied. VDOF4 = VMONO - VMute VMONO : DC voltage at LOT and ROT pins User mode : External input NDT pin: 6 V DC is applied. VMute : DC voltage at LOT and ROT pins User mode : Mute (write register 06H, D1: 0) NDT pin: 6 V DC is applied. VSR1L = 20 log (VL1 / VEL) VL1: Output voltage of LOT pin VEL: Input voltage of EL1, EL2 pins (100 Hz, 150 mVrms) ER1, ER2 pins: No signal Surround: ON (Subaddress 04H, Bit D6: 1) VSR2L : 20 log (VL2 / VEL) VL2: Output voltage of LOT pin VEL: Input voltage of EL1, EL2 pins (1 kHz, 150 mVrms) ER1, ER2 pins: No signal Surround: ON (Subaddress 04H, Bit D6: 1) VSR3L : 20 log (VL3 / VEL) VL3: Output voltage of LOT pin VEL: Input voltage of EL1, EL2 pins (10 kHz, 150 mVrms) ER1, ER2 pins: No signal Surround: ON (Subaddress 04H, Bit D6: 1) VSR4R : 20 log (VR / VEL) VR: Output voltage of ROT pin VEL: Input voltage of EL1, EL2 pins (1 kHz, 150 mVrms) ER1, ER2 pins: No signal Surround: ON (Subaddress 04H, Bit D6: 1) User Mode Note Mute to Stereo Inter-mode DC offset 3 VDOF3 Mute to SAP1 Inter-mode DC offset 4 VDOF4 Mute to External input Surround output characteristics 1 VSR1L External input 1 External input 2 Surround output characteristics 2 VSR2L Surround output characteristics 3 VSR3L Surround output characteristics 4 VSR4R Note For details about the User Mode, refer to 5. MODE MATRIX. Data Sheet S13417EJ2V0DS00 53 PC1851B (7/8) Parameter Symbol Test Conditions Subaddress Data User Mode Note Low frequency band width boost control VBB Low frequency band width cut control VBC Bass response = 20 log (VOUT / VIN) VIN: Input signal level (sine wave: 100 Hz, 150 mVrms) of external input 1 (EL1, ER1 pins) or external input 2 (EL2, ER2 pins) VOUT: Output signal level of LOT, ROT pins 09H 3FH 00H External input 1, External input 2 High frequency band width boost control VTB High frequency band width cut control VTC Treble response = 20 log (VOUT / VIN) VIN: Input signal level (sine wave: 10 kHz, 150 mVrms) of external input 1 (EL1, ER1 pins) or external input 2 (EL2, ER2 pins) VOUT: Output signal level of LOT, ROT pins 0AH 3FH 00H Volume attenuation 1 ATTVL1 Volume attenuation 2 ATTVL2 Volume attenuation = 20 log (VOUT / VIN) VIN: Input signal level (sine wave: 1 kHz, 500 mVrms) of external input 1 (EL1, ER1 pins) or external input 2 (EL2, ER2 pins) VOUT: Output signal level of LOT, ROT pins 07H 3FH 20H External input 1, External input 2 Volume attenuation 3 ATTVL3 Balance attenuation = 20 log (VOUT / VIN) VIN: Input signal level (sine wave: 1 kHz, 500 mVrms) of external input 1 (EL1 pin) or external input 2 (EL2 pin) VOUT: Output signal level of LOT pin Balance attenuation = 20 log (VOUT / VIN) VIN: Input signal level (sine wave: 1 kHz, 500 mVrms) of external input 1 (ER1 pin) or external input 2 (ER2 pin) VOUT: Output signal level of ROT pin Error between channels = 20 log (VROUT / VRIN) - 20 log (VLOUT / VLIN) External input 1 VROUT: Output signal level of ROT pin VRIN: Input signal level of ER1 pin (sine wave: 1 kHz, 500 mVrms) VLOUT: Output signal level of LOT pin VLIN: Input signal level of EL1 pin (sine wave: 1 kHz, 500 mVrms) External input 2 VROUT: Output signal level of ROT pin VRIN: Input signal level of ER2 pin (sine wave: 1 kHz, 500 mVrms) VLOUT: Output signal level of LOT pin VLIN: Input signal level of EL2 pin (sine wave: 1 kHz, 500 mVrms) 00H Balance attenuation L-ch 1 Balance attenuation L-ch 2 Balance attenuation L-ch 3 Balance attenuation L-ch 4 Balance attenuation R-ch 1 Balance attenuation R-ch 2 Balance attenuation R-ch 3 Balance attenuation R-ch 4 Difference between monaural L and R output voltage 1 (in case of external input) ATTBL1 ATTBL2 ATTBL3 ATTBL4 ATTBR1 ATTBR2 ATTBR3 ATTBR4 VOLR1 08H 3FH 30H 20H 00H External input 1, External input 2 08H 3FH 20H 10H 00H External input 1, External input 2 07H 3FH External input 1, External input 2 Difference between monaural L and R output voltage 2 (in case of external input) VOLR2 20H Difference between monaural L and R output voltage 3 (in case of external input) VOLR3 10H Note For details about the User Mode, refer to 5. MODE MATRIX. 54 Data Sheet S13417EJ2V0DS00 PC1851B (8/8) Parameter Symbol Test Conditions Subaddress Data User Mode Note Crosstalk 3 TV signal External input CT3 CT3 = 20 log (VEXT / VTV) VEXT: Output voltage of LOT or ROT pin when the input select 1 is set to the external input 1 or 2 (the data of bits D6 and D5 of subaddress 06H are "01" or "10"). VTV: Output voltage ROT or LOT pin when the input select 1 is set to the TV signal (the data of bits D6 and D5 of subaddress 06H are "00"). COM pin: Monaural, stereo or SAP signal (1 kHz, 100 % modulation) input External input 1 (EL1, ER1 pins), external input 2 (EL2, ER2 pins): No input Measure the values of the external inputs 1 and 2 individually. CT4 = 20 log (VEXTR / VEXTL) VEXTR: Output voltage of ROT pin when the input select 1 is set to the external input 1 or 2 (the data of bits D6 and D5 of subaddress 06H are "01" or "10"). VEXTL: Output voltage LOT pin when the input select 1 is set to the external input 1 or 2 (the data of bits D6 and D5 of subaddress 06H are "01" or "10"). EL1, EL2 pins: External input signal (1 kHz, 500 mVrms) input ER1, ER2 pins: No input Measure the values of the external inputs 1 and 2 individually. THDEXT: Total harmonic distortion rate of LOT, ROT pins External input 1 (EL1, ER1 pins), external input 2 (EL2, ER2 pins): External input signal (1 kHz, 500 mVrms) input VIEM: Maximum input voltage level External input 1 (EL1, ER1 pins), external input 2 (EL2, ER2 pins): External input signal (1 kHz) input when the total harmonic distortion rate of LOT and ROT pins becomes 1 %. NO: Output noise of LOT, ROT pins through DIN/AUDIO External input 1 (EL1, ER1 pins), external input 2 (EL2, ER2 pins): No input (grounded through the resistor (Rg = 600 )) 07H 3FH External input 1, External input 2, Stereo, SAP, Monaural Crosstalk 4 L-ch R-ch CT4 07H 3FH External input 1, External input 2 Total harmonic distortion (in case of external input) THDEXT 07H 3FH External input 1, External input 2 Maximum input voltage of external input VIEM 07H 3FH External input 1, External input 2 Output noise (in case of external input) NO 07H 3FH External input 1, External input 2 Note For details about the User Mode, refer to 5. MODE MATRIX. Data Sheet S13417EJ2V0DS00 55 Test Points A B C D E F G H I J K L-channel fixed output R-channel fixed output External L-channel input 1 External R-channel input 1 External L-channel input 2 External R-channel input 2 L-channel Matrix output R-channel Matrix output L-channel output R-channel output fH monitor Composite signal input DVDD (+5 V) Microcontroller DGND peripheral block SDA SCL A B C D E F G H I J 56 Data Sheet S13417EJ2V0DS00 9. TEST CIRCUIT FOL FOR LPRS520-35 (88PJ) AGND JP DGND VDD Connector for cable 0.1 F FOL AGND VCC FOR EL1 ER1 EL2 ER2 MOL MOR LOT ROT L PC78M05AHF 0.1 F DGND SDA Microcontroller/PC change-over switch SCL VCC K PC1851B peripheral block FHM COM DVDD DGND (+5 V) SCL SDA EEPROMTM block L DVDD DGND (+5 V) SDA(P) SDA SCL(P) SCL IN(P) PC connector Interface block PC1851B Overall surface digital GND Overall surface analog GND COM PC1851B PC1851B Peripheral Block 10 k 10 k 6.8 k 1 M + Note 4 6 123 + + 10 F 3 k 91 k - + FHM - + PC842C (1/2) 10 F 30 k 10 F PC842C (1/2) PC1851B VCC 22 F 0.1 F 1 k 4.7 F COM + 1 + VCC VRE PD1 PD2 MOA FOL FOR EL1 ER1 EL2 ER2 MOL MOR LBC LTC TLO RBC RTC TRO SUR LOT ROT DGND SCL SDA + 1 F 2.2 F + 42 + 2 3 4 41 40 + 2.2 F FOL FOR EL1 ER1 EL2 ER2 MOL MOR 2.2 F 2.2 F 2.2 F 2.2 F 2.2 F 2.2 F 0.1 F 2200 pF 2.2 F 0.1 F 2200 pF 2.2 F 0.022 F 10 F 10 F 1 F + 5 6 + D1 D2 COM SDT NDT SOT SI SOA STI SRB ITI WTI WRB dO VOL-C VOA AGND 39 + 38 + 2.2 F 0.047 F 0.47 F 68 k 0.1 F 1 F 3.3 F ** 3 k + 37 + 7 8 36 + 35 + 0.1 F + 9 10 11 12 + 34 + 33 32 + 31 + 13 14 15 + 30 29 + + 1 F 16.6 k * 10 F ** + 5.1 k 1 F 4.7 F 1 F 28 27 + 16 17 + + + 26 + LOT ROT DGND SCL SDA 18 19 20 25 24 23 22 AGND 21 Note Filter: 126XGS-7990Z, TOKO Remark Use the followings for external parts. Resistor (*): Metal film resistor (1 %). Unless otherwise specified; 5 % Capacitors (**): Tantalum capacitor (10 %). Unless otherwise specified, 20 % Data Sheet S13417EJ2V0DS00 57 PC1851B 10. PACKAGE DRAWINGS 42-PIN PLASTIC SDIP (15.24mm(600)) 42 22 1 A J I 21 K L F D H G N M C M B R NOTES 1. Each lead centerline is located within 0.17 mm of its true position (T.P.) at maximum material condition. 2. Item "K" to center of leads when formed parallel. ITEM A B C D F G H I J K L M N R MILLIMETERS 39.13 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.85 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.72 MAX. 15.24 (T.P.) 13.2 0.25 +0.10 -0.05 0.17 015 P42C-70-600B-2 58 Data Sheet S13417EJ2V0DS00 PC1851B 11. RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "Semiconductor Device Mounting Technology Manual" (C10535E). PC1851BCU: 42-pin plastic SDIP (15.24 mm (600)) Process Wave soldering (only to leads) Conditions Solder temperature: 260 C or below, Flow time: 10 seconds or less Pin temperature: 300 C or below, Heat time: 3 seconds or less (per each lead) Partial heating method Caution The wave soldering process must be applied only to leads, and the make sure that the package body does not get jet soldered. Data Sheet S13417EJ2V0DS00 59 PC1851B Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. EEPROM is a trademark of NEC Corporation. * The information in this document is current as of May, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 |
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